Echelon Product Alerts
Problem: Unexpected behavior when using the SPI Clock Setting of 3 or 4 with the FT 5000 Smart Transceiver or Neuron 5000 Processor Solution: Increase the SPI I/O model FIFO depth |
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Date
December 13, 2010
Products Affected
FT 5000 Smart Transceiver (Model No: 14235R) and Neuron® 5000 Processor (Model No: 14305R)
Summary
An FT 5000 Smart Transceiver or a Neuron 5000 Processor running Neuron firmware version 19 can exhibit unexpected behavior when using the Synchronous Peripheral Interface (SPI) I/O model in a Neuron C program in certain configurations.
Specifying an SPI clock setting of 3 or 4 (using the Neuron C clock(3) or clock(4) keywords in the SPI I/O model declaration) can cause intermittent data loss. The problem could also occur at other SPI clock rate settings. The problem occurs only when transmitting data, but can occur for an FT 5000 Smart Transceiver or a Neuron 5000 Processor running as an SPI master device or as SPI slave device.
The problem arises because the default software size setting for the hardware transmit first-in/first-out (FIFO) structure is too small to process both received data and transmitted data within the time window defined by the SPI clock rate setting. The solution is to increase the software size setting for the transmit FIFO.
For more information about the SPI I/O model, see the I/O Model Reference for Smart Transceivers and Neuron Chips (078-0392-01B).
Solution
Use the following function in your Neuron C program to specify a non-zero transmit FIFO depth for the hardware SPI FIFO:
_io_spi_fifo (tx_level)
This function specifies a value for the transmit FIFO depth of the SPI I/O model's hardware FIFO. Valid values are in the range 0 to 15. The default depth is 0.
tx_level is an unsigned int that specifies the transmit FIFO depth to be used by the hardware transmit FIFO.
The transmit FIFO depth setting is not retained across device reset, so you should include the _io_spi_fifo (tx_level) function in your application's when (reset) clause.
Recommendation: Specify tx_level as 15 to define the maximum transmit FIFO depth.
By default, the transmit FIFO depth is set to zero. Using this function allows you to specify a non-zero transmit FIFO depth.
Example
extern system far void _io_spi_fifo(unsigned tx_level);
IO_8 spi master clock(4) ioSpi;
unsigned int tx_fifo_depth = 15;
unsigned short rc;
char outputString[] = "Hello SPI World!\r\n";
when (reset) {
...
_io_spi_fifo(tx_fifo_depth);
...
}
when (...) {
rc = io_out(ioSpi, outputString, 18);
}
when (io_out_ready(ioSpi)) {
unsigned short spiEerror;
spiEerror = spi_get_error(ioSpi);
if (spiEerror) {
// Process SPI error
...
}
else {
// Process end of SPI transmission
...
}
}
If you require further assistance, please contact the nearest Echelon support office.