Echelon Product Alerts
Precautions when using external oscillators with FT 3120® and FT 3150® Free Topology Smart Transceivers and Cypress Neuron® Chips |
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Date
January 6, 2005
Products Affected
FT 3120 and FT 3150 Free Topology Smart Transceivers and Cypress Neuron Chips when used with an external oscillator that drives the CLK1 input pin.
Summary
The presence of a high-frequency CLK1 transient at power-up could cause the Neuron Chip’s internal Flash memory to lock-up. Lock-up can occur if both the CLK1 high-frequency transient is higher than the maximum allowed input clock frequency for the Neuron Chip, and if that high-frequency transient is present at the same time that the Vdd power supply voltage is ramping up through the internal LVI trip threshold. Flash lock-up can occur even if the Neuron Chip is held in reset during the power-on transient.
Some external oscillators exhibit a high-frequency transient behavior at their clock output pin during the power-up transient. This happens when the oscillator circuit initially powering up at a harmonic frequency, and then settling down to the correct frequency within some start-up time. This start-up time is often a parameter specified on the oscillator data sheet.
When the high-frequency transient is higher than the maximum allowed input clock frequency for the Neuron Chip, and when the transient occurs at the same time that the Vdd power supply for the Neuron Chip is passing through the internal LVI trip threshold, a potential exists for the chip’s internal Flash memory to lock-up, causing the chip to enter a continuous Watch Dog Timer (WDT) reset state. If the Vdd power-up transient is smooth with no ripple as Vdd passes through the internal LVI circuit’s threshold, then this lock-up state does not occur.
The presence of ripple on Vdd, such as from a switching power supply, causes the LVI to first release reset as Vdd climbs up above the upper LVI trip threshold, and then briefly re-assert reset when Vdd ripples down through the lower LVI trip voltage, and then release reset again when Vdd ripples back above the upper LVI threshold. The coincidence of these LVI trips and the too-high CLK1 input frequency can cause the internal Flash memory lock-up to occur, which results in a continuous WDT reset state. Holding the chip in reset during power-up does not prevent this behavior, and an external reset does not recover the device once the WDT reset state is entered. The lock-up state may be cleared by power-cycling the Neuron Chip. The maximum allowed CLK1 frequency and the LVI trip voltage level are listed in the respective Neuron Chip and Free Topology Smart Transceiver data sheets.
Workarounds
The following workarounds are recommended:
- Use the Neuron Chip’s internal clock oscillator circuit with an external crystal, instead of using an external oscillator that can possibly provide a CLK1 input transient that is higher than the maximum frequency allowed.
Note that when the Neuron Chip’s internal oscillator circuit is used with an external crystal, the lock-up problem does not occur. The CLK2 clock output pin of a Neuron Chip can drive one external CMOS load, so the preferred clock implementation is to use the Neuron Chip with an external crystal, and then use the CLK2 output for any external clocks that are needed. CLK2 can be buffered with an external gate if it is needed for more than one CMOS input.
- Use a linear power supply instead of a switching power supply.
Note that when the Vdd rail passes smoothly through the upper trip voltage of the Neuron Chip’s internal LVI (see the appropriate data sheet or data book for this trip voltage), lock-up does not occur. The internal LVI has enough hysteresis to avoid re-tripping when a linear power supply is used for Vdd. However, when a switching power supply is used to generate Vdd, there is generally enough ripple on Vdd to cause the multiple trips of the LVI as Vdd passes though the trip threshold voltage on power-up. In cases where an external oscillator must be used to power the FT 3120 or FT 3150 Free Topology Smart Transceiver or any Cypress Neuron Chip, the use of a linear power supply is highly recommended over use of a switching power supply.
- Use an external oscillator that definitely does not exhibit the high-frequency transient behavior at power-up, if you need to use an external oscillator.
Some external oscillators do not exhibit the high-frequency transient behavior at power-up. Designers should consult with the manufacturer of the external oscillator that they intend to use, in order to choose an oscillator vendor and specific part that does not generate high-frequency transients at power-up. CLK1 input frequencies must not be above the maximum allowed clock input frequency for the Neuron Chip in the design. See the appropriate Neuron Chip data sheet or data book for the maximum allowed CLK1 frequency.